The present invention relates to wafer debonding and, more specifically, to advanced methods for handling wafer debonding.
Three-dimensional (3D) chip technologies include 3D integrated circuits (IC) and 3D packaging. 3D chip technologies are gaining widespread importance as they allow for greater integration of more complex circuitry with shorter circuit paths allowing for faster performance and reduced energy consumption. In 3D ICs, multiple thin silicon wafer layers are stacked and interconnected vertically to create a single integrated circuit of the entire stack. In 3D packaging, multiple discrete ICs are stacked, interconnected, and packaged together.
Modern techniques for 3D chip technologies, including both 3D ICs and 3D packaging, may utilize through-silicon vias (TSV). A TSV is a vertical interconnect access (VIA) in which a connection passes entirely through a silicon wafer or die. By using TSVs, 3D ICs and 3D packaged ICs may be more tightly integrated as edge wiring and interposer layers are not required.
Temporary wafer bonding/debonding is an important technology for implementing TSVs and 3D silicon structures in general. Bonding is the act of attaching a silicon device wafer, which is to become a layer in a 3D stack, to a substrate or handling wafer so that it can be processed, for example, with wiring, pads, and joining metallurgy, while allowing the wafer to be thinned, for example, to expose the TSV metal of blind vias etched from the top surface.
Debonding is the act of removing the processed silicon device wafer from the substrate or handling wafer so that the processed silicon device wafer may be added to a 3D stack.